1. Field of the Invention
The present invention relates generally to semiconductor memory devices and more particularly to a method and apparatus for high speed testing of semiconductor memory devices.
2. Description of the Related Art
A typical semiconductor memory device includes a memory cell array for storing data, and peripheral circuits for controlling the transfer of data to and from the memory cell array. It is essential to test each unit memory cell in the memory cell array and also the individual peripheral circuits for proper operation to realize a perfect semiconductor memory device. Most defective semiconductor memory devices contain a single bad bit. The established method of testing a memory device requires reading each bit individually to test for defects. However, this test method takes an excessive amount of time and is very expensive.
More recently, multi-bit parallel testing methods which test multiple memory cells during one access cycle have been developed. It is especially important to shorten the test time and reduce test costs when testing high capacity memory device with capacities over 256 Mbit. Therefore, many companies and research organizations have been working to develop new testing methods.
One such method appeared in the NEC's VLSI circuits symposium in 1993 and will be described with reference to FIGS. 1, 2 and 3. Referring to FIG. 1, the data output path of a semiconductor memory device has a sub-word line driver. Multiple sub-word line drivers SWD are connected to a main word line MWL which is connected to the output port of a row decoder which is not shown in this drawing. The sub-word lines SWL are connected to each end of the sub-word line drivers SWD. Pairs of bit lines are arranged vertically on each sub-word line SWL. One bit line sense amplifier SA is connected to each pair of bit lines. The output port of each bit line sense amplifier SA is connected to the input port of a column decoder YDEC through a data line DL. Multiple output sense amplifiers DA are connected to the output port of each column decoder YDEC. The output sense amplifiers are connected to input/output lines IO respectively. The output port of an input buffer and the input port of an output buffer are connected to each input/output line I/O. The input port of the input buffer and the output port of the output buffer are connected together to one input/output.
FIG. 2 is a schematic diagram of a test circuit for use with the memory device of FIG. 1. The array blocks associated with each sub-word line driver are selected by output signals from shift registers SR. The output signals of shift registers SR are synchronized with an internal clock and are output sequentially in a regular manner. In an array block connected to a sub-word line driver SWD, there are multiple (N in the example of FIG. 2) output sense amplifiers DA. The output sense amplifier DA is operated by a control signal DAE from an input/output control circuit DAC which responds to the output signal of the shift register.
FIG. 3 is a timing diagram showing waveforms of various signals associated with the circuits of FIGS. 1 and 2. A typical test process will be explained with reference to FIGS. 1, 2, and 3. One test cycle is initiated by the activation of the section row address strobe signal /RAS. The sub-word lines SWL are enabled sequentially by the internal clock ICLK during the test. The control signal DAE to each output sense amplifier DA is synchronized with a pulse of the internal clock signal in the test cycle. The output from output sense amplifier DA is read in a short cycle. By using a high frequency counter and controlling the word line enable, the bit line sensing, and the data line sensing, the data can be output sequentially during a short cycle. Thus, the output time required for conducting the test is reduced.
However, a problem with this prior art technique is that the large number of sense amplifiers in each array block (N in FIGS. 1 and 2) increases the layout area, and thus the cost, of the chip.
Another problem with the prior art test arrangement is that it increases the difficulty of designing the chip. The additional circuits needed for the sub-word line driver, shift register, bit line sensing circuitry, and data line sensing circuitry increase the layout area of the chip and interrupts the integration process.
A further problem with the test arrangement of FIGS. 1 and 2 is that the output sense amplifier must be enabled and disabled selectively by the shift register which requires at least 7 nanoseconds. Therefore it is difficult to operate the semiconductor memory device at high speeds.
Yet another problem with the prior art test method is that is consumes excessive electric power. Data is typically accessed 16-bits at a time during normal operation for one access cycle. However, to test 256 memory cells at one time, 256 input/output lines are needed, and 256 output sense amplifiers must operate at the same time. This causes excessive power consumption.
Accordingly, a need remains for a technique for high speed testing of a highly integrated semiconductor memory device which overcomes the problems discussed above.